The present invention relates to a local IDE (Integrated Drive Electronics) bus architecture for use in computer technology.
Computer technology has made dramatic progress in recent years. Presently available microprocessors can run ten times faster than five years ago. However, the bus architecture of the current PC has not been changed significantly since IBM introduced the PC AT in the 1980s.
For example, consider the very popular ISA (Industry Standard Architecture) bus whose bandwidth is about 8 MBYTE/s for memory access and 5.3 MBYTE/s for I/O (Input/Output) access. Compare the ISA bus to a 33 MHz 80386DX microprocessor whose bus bandwidth is 132 MBYTE/s. The ISA speed calculation is based on a 8 Mhz bus clock, 2 clocks/memory cycle, 3 clocks/I/O cycle and 16 bits data width. With existing system architectures, the performance of peripheral devices like an IDE (Integrated Drive Electronics) drive would eventually be limited by the ISA bandwidth and the overhead of transferring a host cycle to the ISA.